3D binary and 3D transistor/resistor 3D binary square 4 and triangle 3 goes into every number except 1 2 and 5 at the beginning of a binary ....which is common some numbers have more than one combination triangles and squares make every 3D shape even a sphere example 10 = 1 square and 2 triangles which makes a pyramid and x amount of pyramids makes a sphere 3D shapes can carry anything ...software frequencies video energy

3D transistor/resistor the space between two number like 1 and 2 is 1 and quarter 1 and half exc but the space between two number that are the same is big and fast.....example 10 ................................2x5=10pulse10=5x2..........................................................................same number different addresses if u use the formula with 3D shapes it can carry anything ...if u make a transistor with all the possible shapes using numbers....it can correspond with the same numbers with the times table numbers and go thro the space/pulse

Nice analysis but in the end the larger ecosystem and value proposition for Apple, Qualcomm, MediaTek, Intel, AMD, Nvidia and others matter than raw transistors density.

They are generational important. Look at Intel 10nm looks great at IEDM, ask the Canon and Icelake teams and Intel in general how that ended up! Similar look at the A and M chips from Apple, Qualcomm and MediaTek how are things.

It’s a larger business and things like Fin Pitch, SDB and metal pitch matter but if you can’t ramp and ship on schedule with good yields it matters not.

Intel N4 as rebranded from a density and feature looks good as likely their subsequent nodes will T IEDM and VLSI. Sadly those are conferences and IBM in their day had good stories too. Sadly intel track record for actually deliver is yet to be seen and sketchy based on the past five years of launches. Lastly they simply won’t have enough EUV even if everything else works perfectly for them

>Samsung’s 4LPE (H200g54) at 136.5 MTr/mm² is ever so slightly less dense than N5 but arrived 16 months later at vastly lower volumes and low reported yields. Density is only 1 metric in PPA (Power, Performance, Area). Samsung closed the gap in density but performance and power remain behind, with only a small improvement over their 7nm-class node.

Is there an article where you analyse Samsung's 4LPE node and where did you get the figure from?

Great write-up. The elephant in the room is 'Why would TSMC cite theoretical density, if they are actually producing significantly less dense chips?', and the answer is simple, they want investors and clients to believe they are further ahead of the competition (Intel, Samsung) than they actually are. With the TSMC coming in with lower than expected density, N3 delays and missing targets, it has given Intel and Samsung room to catch-up. Looking at the Intel 4 & 3 data we have, realistically we will see Intel meeting TSMC in density in late 2023 when Intel 3 hits risk production.

## The TRUTH of TSMC 5nm

3D binary and 3D transistor/resistor 3D binary square 4 and triangle 3 goes into every number except 1 2 and 5 at the beginning of a binary ....which is common some numbers have more than one combination triangles and squares make every 3D shape even a sphere example 10 = 1 square and 2 triangles which makes a pyramid and x amount of pyramids makes a sphere 3D shapes can carry anything ...software frequencies video energy

3D transistor/resistor the space between two number like 1 and 2 is 1 and quarter 1 and half exc but the space between two number that are the same is big and fast.....example 10 ................................2x5=10pulse10=5x2..........................................................................same number different addresses if u use the formula with 3D shapes it can carry anything ...if u make a transistor with all the possible shapes using numbers....it can correspond with the same numbers with the times table numbers and go thro the space/pulse

#3barbaraschrepel

Is it true that the advertised 4nm on snapdragon 8 gen 1 is actually 5nm? What is the density of that proccess?

Nice analysis but in the end the larger ecosystem and value proposition for Apple, Qualcomm, MediaTek, Intel, AMD, Nvidia and others matter than raw transistors density.

They are generational important. Look at Intel 10nm looks great at IEDM, ask the Canon and Icelake teams and Intel in general how that ended up! Similar look at the A and M chips from Apple, Qualcomm and MediaTek how are things.

It’s a larger business and things like Fin Pitch, SDB and metal pitch matter but if you can’t ramp and ship on schedule with good yields it matters not.

Intel N4 as rebranded from a density and feature looks good as likely their subsequent nodes will T IEDM and VLSI. Sadly those are conferences and IBM in their day had good stories too. Sadly intel track record for actually deliver is yet to be seen and sketchy based on the past five years of launches. Lastly they simply won’t have enough EUV even if everything else works perfectly for them

>Samsung’s 4LPE (H200g54) at 136.5 MTr/mm² is ever so slightly less dense than N5 but arrived 16 months later at vastly lower volumes and low reported yields. Density is only 1 metric in PPA (Power, Performance, Area). Samsung closed the gap in density but performance and power remain behind, with only a small improvement over their 7nm-class node.

Is there an article where you analyse Samsung's 4LPE node and where did you get the figure from?

Great write-up. The elephant in the room is 'Why would TSMC cite theoretical density, if they are actually producing significantly less dense chips?', and the answer is simple, they want investors and clients to believe they are further ahead of the competition (Intel, Samsung) than they actually are. With the TSMC coming in with lower than expected density, N3 delays and missing targets, it has given Intel and Samsung room to catch-up. Looking at the Intel 4 & 3 data we have, realistically we will see Intel meeting TSMC in density in late 2023 when Intel 3 hits risk production.