Those look like memory-side caches per DDR5 interface, not L3 cache. Like on Apple M1 Pro.
The difference, if the placement clue is correct, is that MSC contains only values located in the associated DDR5. This eliminates a lot of coherency overhead, although it can also include directory information to track which L2 caches might hold values.
Lucky if it is seen in 2024.
Those look like memory-side caches per DDR5 interface, not L3 cache. Like on Apple M1 Pro.
The difference, if the placement clue is correct, is that MSC contains only values located in the associated DDR5. This eliminates a lot of coherency overhead, although it can also include directory information to track which L2 caches might hold values.