In this interview AMD says downlink between CPU to chipset is PCIe 5.0 : https://www.techpowerup.com/review/amd-zen-4-ryzen-7000-technical-details/

Why you say it's PCIe 4.0 ?

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We say it in this article as well! 4 of the 28 lanes of PCIe 5.0 from the CPU are used for chipset downlink. But the chipset itself only supports PCIe 4.0 uplink, therefore the connection runs at PCIe 4.0.

As explained in our 1st article, AMD Ryzen CPUs do not need a chipset to run. They can use an activator like X300 that does not use any PCIe lanes. Possible that future uses of the IO Die may expose all 28 lanes at full PCIe 5.0 linkrate.


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Siena? That's Something6 i guess?

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